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- Vol. 3 Issue 2
- Article
Network on Chip and Its Low Power Techniques
Authors
1Research Scholar, Department of EEE, Kumaraguru College of Technology, Coimbatore, Tamilnadu, India. 2Professor, Department of EEE, Kumaraguru College of Technology, Coimbatore, Tamilnadu, India.
Article Information
- Published In
- Volume 3, Issue 2 (2024)
- Published Online
- May-August 2024
- Pages
- 55-59
- Article Type
- Research Article
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Abstract
View PDFThe advent of Network-On-Chip (NoC) architecture has significantly revolutionized the design of complex System-On-Chip (SoC) systems by providing scalable and efficient communication infrastructures. NoC architectures offer advantages such as high bandwidth; low latency and better scalability compared with traditional bus-based communication architectures. However, the ever-increasing demand for higher performance and lower power consumption poses significant challenges for NoC designers. This article reviews the basic architectures and design issues of NoCs with SoCs and further extended with research challenges and low power techniques.
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